Safety-critical systems are important parts of our daily life. Those systems are also called dependable systems, as our lives can depend on them. Examples are navigation controllers in an aeroplane, breaking controller in a car, or a train control system. Those safety-critical systems need to be certified and the maximum execution time needs to be bounded and known so that response times can be assured when critical actions are needed. Note that just using a faster processor is not a solution for time predictability. Even with high performance processors in our desktop PCs we notice once in a while that the PC is “frozen” for a few seconds. For word processing we accept this minor inconvenience, but for a safety-critical system such a “pause” can result in a catastrophic failure.
The T-CREST project will research and develop tools and build a system that prevents pauses by identifying and addressing the causes for possible pauses. The T-CREST time-predictable system will simplify the safety argument with respect to maximum execution time striving to double performance for 4 cores and to be 4 times faster for 16 cores than a standard processor in the same technology (e.g. FPGA). Thus the T-CREST system will result in lower costs for safety relevant applications reducing system complexity and at the same time faster time-predictable execution.
Standard computer architecture is driven by the following paradigm: make the common case fast and the uncommon case correct. This design approach leads to architectures where the average-case execution time is optimized at the expense of the worst-case execution time (WCET). Modelling the dynamic features of current processors, memories, and interconnects for WCET analysis often results in computationally infeasible problems. The bounds calculated by the analysis are thus overly conservative.
We need a sea change and we shall take a constructive approach by designing computer architectures where predictable timing is a first-order design factor. For real-time systems we propose to design architectures with a new paradigm: make the worst-case fast and the whole system easy to analyze. Despite the advantages of analyzable system resources, very few research projects exist in the field of hardware optimized for the WCET.
Within the project we will propose novel solutions for time-predictable multi-core and many-core system architectures. The resulting time-predictable resources (processor, interconnect, memories, etc) will be a good target for WCET analysis and the WCET performance will be outstanding compared to current processors. Time-predictable caching and time-predictable chip-multiprocessing (CMP) will provide a solution for the need of more processing power in the real-time domain.
Next to the hardware (processor, interconnect, memories), a compiler infrastructure will be developed in the project. WCET aware optimization methods will be developed along with detailed timing models such that the compiler benefits from the known behaviour of the hardware.
Expected market impact
Embedded systems are taking over control in always more demanding environments, including safety and security critical systems. The robustness and safety of systems is therefore an ever-growing competitiveness factor. The aptitude to produce robust predictable systems at a competitive price will be key to keeping European companies at the cutting edge of the embedded system market. A large number of European companies will benefit via the project coordinator, The Open Group having close links to more than 400 member companies involved in technology evolution. Direct impact on the market position of 3 European companies participating in the project is expected, namely the tools company AbsInt as well as GMV and INTECS offering safety critical solutions for Aeronautics and Transport. T-CREST will also help European industry to build reliable systems, not only in the areas of air and ground transportation, but also in many other areas where robustness, availability and safety are important requirements to the embedded systems.