Sahar Abbaspour and Florian Brandner
Junior Researcher Workshop on Real-Time Computing (JRWRTC)
to appear

Abstract

Modern computer architectures use features which often complicate the WCET
analysis of real-time software. Alternative time-predictable designs, and
in particular caches, thus are gaining more and more interest. A recently
proposed
stack cache, for instance, avoids the need for the analysis of complex cache
states. Instead, only the occupancy level of the cache has to be determined.

The memory transfers generated by the standard stack cache are not generally
aligned. These unaligned accesses risk to introduce complexity to the
otherwise simple WCET analysis. In this work, we investigate three different
approaches to handle the alignment problem in the stack cache: (1) unaligned
transfers, (2) alignment through compiler-gen\-erated padding, (3) a novel
hardware extension ensuring the alignment of all transfers. Simulation results
show that
our hardware extension offers a good compromise between average-case performance
and analysis complexity.